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 自动化学报  2017, Vol. 43 Issue (8): 1412-1417 PDF

1. 武汉大学电气工程学院太阳能高效利用湖北省协同创新中心 武汉 430072;
2. 国家电网上海市电力公司信息通信公司 上海 200010;
3. 国家电网北京市电力公司 北京 100031

Influence of Converter Bus Serious Harmonic Distortion on HVDC Transmission System
Ziyu Guo1, Tao Lin1, Gengtao Jia2, Liyong Wang3
1. Solar Energy Efficient Use Collaborative Innovation Center, School of Electrical Engineering, Wuhan University, Wuhan 430072, China;
2. State Grid Shanghai Information and Telecommunication Company, Shanghai 200010, China;
3. State Grid Beijing Electric Power Company, Beijing 100031, China
Abstract: Possibility of serious harmonic distortion (SHD) increases as multi-infeed direct current (MIDC) transmission develops rapidly in recent years. In this paper, the mechanism of high voltage direct current (HVDC) controller working against SHD is proposed for theoretical derivation of phase locked loop (PLL) output and valve commutation process. To reduce static error of constant extinction angle (CEA) controller and enhance active power transmission, the insertion of current error (CE) controller into CEA is minified. A calculation of inverter operating point is proposed in the end. The correctness of mechanism and algorithm is verified through power systems computer aided design (PSCAD) simulation.
Key words: High voltage direct current (HVDC)     converter     harmonics     serious harmonic distortion (SHD)     phase locked loop (PLL)     constant extinction angle (CEA)
1 Introduction

Converter of high voltage direct current (HVDC) system turns into harmonic resource when it works with unbalanced AC voltage. Previous studies have focused on this phenomenon. According to [1], the 3rd harmonic current of inverter in international council on large electric systems (CIGRE) benchmark model can be as high as 0.469 kA in unbalanced situation. However, the operation of converter working in such serious harmonic distortion (SHD) condition lacks research, for the electrical coupling between converters is usually weak in the past. With the vigorous development of multi-infeed HVDC project in China, converters may be close to each other in HVDC placement area like Shanghai and Guangzhou. Possibility of converter working in SHD keeps growing in such areas [2]. Researches on converter operation in SHD are quite necessary.

Reference [3] analyzed the dynamic process of converter when asymmetrical problem happened in AC system, in which unbalanced conduction time and commutation angle between phases are considered. It calculated the harmonics generated by the converter. However, it did not elaborate the converter operation point calculation method. Reference [1] took the controller characteristic into consideration and found a way to calculate the operation point, but no further study on how other converters are affected by the harmonic current is proposed. Other studies on HVDC harmonics focused mainly on the transformation of harmonic order. Reference [4] analyzed transformation of converter bus harmonics in presence of harmonic voltage. Negative correlation between the dominant harmonic amplitude and phase-change angle is certified, however, only through simulation. References [5]-[7] determined the series relationship of harmonic impedance between DC and AC sides in HVDC system by defining DC and AC equivalence harmonic impedance, through which the frequency point resonance most likely to occur is calculated. However, only small signal model is applied in above references, where harmonics did not affect the operation point of DC system. There is no doubt that one converter will affect the control system of another by the harmonic current it generates. The operation point of the HVDC would be shifted as well. Numeric simulation software (PSCAD/EMTDC, etc.) can tell variety of DC/AC system characteristics under SHD. However, it is not enough to explain the inner theory of such phenomena.

In this paper, operation of HVDC system with SHD on converter bus is analyzed. Aiming the fact that constant extinction angle (CEA) controller cannot trace the setting value under SHD, an improved control scheme is proposed, with which steady-state error of CEA and power consumption in DC transmission are largely reduced. A calculation method of HVDC operation point in SHD is proposed in the end. The conclusion correctness is verified through PSCAD/EMTDC simulation.

2 Analysis of Converter Operation Working in SHD

The CIGRE-benchmark model [8] applied in this paper is shown in Fig. 1. Inverter side SHD is created by paralleling harmonic power source beside the inverter bus. Constant current controller (CC), CEA controller and voltage dependent current order limited (VDCOL) controller constitute the control system.

 Figure 1 HVDC CIGRE-benchmark model.

According to [1] and [3], third harmonic current in AC side is the main harmonic order converter injection due to unbalanced AC voltage. Taking inverter bus voltage third harmonic as the objective, the following analysis focuses on SHD influence on HVDC system, including PLL and CEA controller. HVDC control system operation characteristics in SHD are then concluded. A calculation method of HVDC operation point in SHD is proposed in the end.

2.1 Analysis of Converter Bus Waveform in SHD

The expressions of converter bus voltage, also known as point of common coupling (PCC), with harmonics are in (1) [9]

 \begin{align} &U_a=U_ 1\sin(\omega t)+\sum\limits_{h=2}U_h \sin(h\omega t+\phi_h) \nonumber\\ &U_b=U_ 1\sin(\omega t+120^{\circ})+\sum\limits_{h=2}U_h \sin(h\omega t+\phi_h+120^{\circ}) \nonumber\\ &U_c=U_ 1\sin(\omega t+240^{\circ})+\sum\limits_{h=2}U_h \sin(h\omega t+\phi_h+240^{\circ})\nonumber\\ \end{align} (1)

where $U_h$ represents h-order harmonic amplitude while $\phi_h$ represents its initial phase. In normal operation, $U_h$ is small with filter. The converter bus voltage acts as fundamental waveform. When specific harmonics exceed, converter bus voltage waveform will be distorted. Taking third harmonic as example, when $U_1=126.81$ kV, $U_3 =8.31$ kV, $\phi_3 =38^{\circ}$, the waveform of converter bus voltage of phase A and C is shown in Fig. 2. Solid line represents distorted waveform while the dashed line represents fundamental waveform.

 Figure 2 Voltage wave when distortion occur.

With 3rd harmonic voltage distortion, the zero crossing points of phase $A$ and $C$ (points where $U_a= U_c$ in the figure) have shifted comparing to the normal operation status. Supposing the moments of line-to-line voltage zero crossing points when distortion happens are $t_1$ and $t_2$, while moments of that when distortion does not happen are $t_1 '$ and $t_2 '$.

The shift of line-to-line voltage zero crossing moment affects the actual size of extinction angle and commutation angle, which are determined by the operating characteristics of phase locked loop (PLL) in the converter firing angle controller.

2.2 Influence of Converter Bus SHD on PLL

Converter firing controller is a control link which achieves operating status adjustment of converter commutation device. Currently, HVDC converter normally uses PLL control system [10]. The operating principle of PLL is shown in Fig. 3. The inserted error in normal operation is:

 \begin{align} % \nonumber to remove numbering (before each equation) e=U_\alpha \cos(\theta)-U_\beta \sin(\theta) \end{align} (2)
 Figure 3 PLL control block.

where

 $\begin{array}{*{35}{l}} {}&{{U}_{\alpha \beta }}=T{{U}_{abc}}\text{ } \\ {}&{{U}_{\alpha \beta }}=\left[\begin{matrix} {{U}_{\alpha }} \\ {{U}_{\beta }} \\ \end{matrix} \right], \qquad T=\frac{2}{3}\left[\begin{matrix} 1&-\frac{1}{2}&-\frac{1}{2} \\ 1&\frac{\sqrt{3}}{2}&-\frac{\sqrt{3}}{2} \\ \end{matrix} \right] \\ {}&{{U}_{abc}}=\left[\begin{matrix} {{U}_{a}} \\ {{U}_{b}} \\ {{U}_{c}} \\ \end{matrix} \right]. \\ \end{array}$ (3)

When only fundamental wave component exists in converter bus voltage, with the above formula, inserted error can be expressed as:

 \begin{align} % \nonumber to remove numbering (before each equation) e=U_1 \sin(\omega t-\theta). \end{align} (4)

In steady state, $e=0$ and theta completely tracks phase $A$ voltage with angular velocity. When three phase voltage of converter bus is distorted (shown in Fig. 2), inserted error e can be expressed as:

 \begin{align} % \nonumber to remove numbering (before each equation) e=U_1 \sin(\omega t-\theta)+U_3 \sin(3\omega t+\phi_3-\theta). \end{align} (5)

In this state, the output theta tracks two components, respectively. The angular velocity $\omega$ tracks the phase of fundamental voltage and 3$\omega$ tracks that of the third harmonic voltages. Considering that $U_1$ is much larger than $U_3$ in (5), the output of the angular velocity remains the fundamental angular velocity with small-scale fluctuations of 2$\omega$. The output of theta in simulation is shown in Fig. 4. Fig. 5 shows the output of PLL frequency when the 3rd harmonic voltage exists.

 Figure 4 The output of $\theta$ by PLL.
 Figure 5 Tracking frequency of PLL in SHD.

Fig. 4 displays that PLL output remains unchanged in SHD. Fig. 5 illustrates the small fluctuations of Fig. 4. The output component of harmonic voltage is insignificant when compared with the fundamental component. In the remaining part of the paper, the impact of the commutation bus distortion on PLL output will not be considered, assuming that the PLL still locks phase-$A$ fundamental voltage.

2.3 Influence of SHD on Commutation Process

The duration of some commutation process is increased by SHD, while others are decreased. This paper still uses the traditional 2-3 mode to describe this process, as is shown in Fig. 6.

 Figure 6 2-3 mode circuit in commutation process.

In the commutation process, there is

 \begin{align} \frac{dI_k}{dt}= \frac{U_a-U_c}{2L_B}. \end{align} (6)

In (6), $I_k$ stands for the loop current rising from 0 to $I_d$. $L_B$ stands for the commutation transformer leakage inductance.

When 3rd voltage exists only, by substituting (1) into (6), we obtain (7)

 \begin{align} \frac{dI_k}{dt}= \frac{\sqrt{6}U_1}{2L_B}\sin\left(\omega t- \frac{\pi}{6}\right)+\frac{\sqrt{6}U_3}{2L_B}\sin\left(3\omega t-\frac{\pi}{6}+\phi_3\right). \end{align} (7)

For PLL still tracks the fundamental frequency, this paper sets the fundamental frequency angle as integration length. As for phase $A$ and $C$, taking ${13\pi}/{6}$ (typical starting phase angle of commutation process) as a starting point of commutation process, there is

 \begin{align} I_d=& \int_{\frac{13\pi}{6}+\alpha}^{\frac{13\pi}{6}+\alpha +\mu} \bigg(\frac{\sqrt{6}U_1}{2L_B}\sin\left(\omega t-\frac{\pi}{6}\right)\nonumber\\& +\frac{\sqrt{6}U_3}{2L_B}\sin\left(3\omega t-\frac{\pi}{6}+\phi_3 \right)\bigg)d\omega t \end{align} (8)

where $\alpha$ stands for the firing angle and $\mu$ stands for commutation angle. By solving (8), we obtain (9)

 \begin{align} I_d=&\ \frac{\sqrt{6}U_1}{2X_B}[\cos(\alpha_I)-\cos(\alpha_I +\mu)] \nonumber\\ & +\frac{\sqrt{6}U_1}{2X_B \times 3}\bigg[\cos\left(\frac{13\pi \times 3}{6}+3\alpha_I+\phi_3\right)\nonumber\\ &-\cos\left(\frac{13\pi \times 3}{6}+3\alpha_I+\phi_3+3\mu\right)\bigg]. \end{align} (9)

$X_B$ stands for the leakage reactance of fundamental voltage. For a more general case, when multiple SHD happens, the six commutation angles of 6-pulse inverter bridge within a cycle can be obtained by the following formula

 \begin{align} & {{I}_{d}}=\frac{\sqrt{6}{{U}_{1}}}{2{{X}_{B}}}[\cos (\alpha )-\cos (\alpha +u)] \\ & +\sum\limits_{h=2}{\frac{\sqrt{6}{{U}_{h}}}{2{{X}_{B}}\times h}}[\cos (\left( \frac{\pi }{2}+m\times \frac{\pi }{3} \right) \\ & \times h+h\times \alpha +{{\phi }_{h}})-\sum\limits_{h=2}{\cos }(\left( \frac{\pi }{2}+m\times \frac{\pi }{3} \right) \\ & \times h+h\times (\alpha +{{u}_{m}})+{{\phi }_{h}})] \\ \end{align} (10)

where $m=1, 2, \ldots, 6.$

3 Influence of SHD on CEA Controller

When SHD happens, there is

 $$$\label{2714910384} \gamma +\mu =180-\alpha -\Delta \alpha$$$ (11)

where $\Delta\alpha$ is the shift angle of $\alpha$ in SHD.

Extinction angle $\gamma$ is an important indicator of the converter safe operation. Physically it means the reverse voltages time for the thyristors to fully recover its blocking capability [11]. If angle $\gamma$ is too small, the thyristor may bear forward voltage soon after commutation. In this case, even no new firing signal is given, thyristor may switch on again, resulting in a DC commutation failure.

3.1 CEA Controller Operation in SHD

CEA aims at maintaining the extinction angle for a given value [12]. It is achieved by adjusting the inverter firing angle. The constant extinction angle controller CIGRE-benchmark model used is structured as Fig. 7:

 Figure 7 CEA control block.

The inverter side firing angle has to decrease in SHD, so as to maintain the minimum of $\gamma$ per cycle to 0.2618 ($15^{\circ}$). The active and reactive power of DC system follows (12) [13]

 \begin{align} &V_{do}=\frac{3\sqrt{2}}{\pi}BTE_{ac}\nonumber\\ &V_d=V_{do} \cos(\pi -\alpha)+\frac{3}{\pi}X_c I_d B\nonumber\\ &\phi= {\arccos}\left(\frac{V_d }{V_{do}}\right)\nonumber\\ &P_d=V_d I_d\nonumber\\ &Q_d=P_d {\rm tan}(\phi). \end{align} (12)

In (12), $E_{ac}$ stands for the AC bus line-to-line RMS voltage. T stands for the transformer turns ratio. $B$ stands for the number of bridges in series. $X_c$ stands for the commutation reactance and $V_d$ stands for the DC voltage. By (12), the inverter side firing angle has to decrease in SHD, thus reducing the economic benefits of DC system.

3.2 Improvements on Current Error Controller

By (12), one way to reduce the loss of transmission capacity is to minimize the decrease of inverter firing order.

The output of current error (CE) controller works as the interference for CEA, reflecting the impact of DC current on commutation process. By the switch function theory, when $h$ order harmonic voltage distortion happens, CE will bring ($h-1$) order harmonic signal into CEA. This brings static error to the output of CEA, leading to the unduly reduction of the firing angle.

It may moderately reduce the output of CE by multiplying it with coefficient m, where $m < 1$, in order to reduce the loss of transmission power.

4 Calculation Method of Inverter Operating Point in SHD

In AC-DC system load flow calculation, by using quasi-steady-state model, the converter can be described as a PQ load. The only difference between pure AC system and AC-DC system flow calculation is that DC element is added to the power equation.

Under the operation of constant current controller and CEA controller, the DC current and the extinction angle remain constant, so the corresponding elements of Jacobian matrix can be easily proposed. However, commutation changes in SHD, according to (10) and (11). The inverter side extinction angle changes periodically. In this case DC quasi-steady-state model does not work well. New methods are needed to determine the operating point of the voltage distorted inverter.

Considering that the inverter side firing angle for fundamental voltage and power remains unchanged, (12) is able to describe the DC active and reactive power, this paper takes firing angle order as parameter in AC/DC flow calculation to get the operating point of the inverter station when distortion happens. Specific procedures are in Fig. 8.

 Figure 8 Calculation flowchart of HVDC operating point in SHD.
5 Verification

When SHD happens, some of the commutation angles are elongated while others are shortened. Thus the extinction angles are correspondingly shortened and elongated. The simulation result of $\gamma$ by PSCAD is illustrated in Fig. 8 with $U_1=126.81$ kV, $U_3=8.31$ kV, $\phi_3=36^{\circ}$ and $\alpha$ $=$ $141.69$. Table Ⅰ is the simulation and calculation result in one cycle. "com-valve" stands for the valves in communication process. "Cal" stands for calculation. "Sim" stands for simulation and "harm" stands for harmonic.

Table Ⅰ Simulation and Calculation Result of $\gamma$ Per Cycle ($^\circ$)

Figs. 10-13 illustrate simulation results of the minimum of $\gamma$ per cycle, firing angle order, power of DC transmission and fundamental line-to-ground RMS voltage of PCC respectively. SHD occurs at 2.5 s. By reducing the output of CE to 20 $\%$, steady-state value of min r is reduced while firing angle, power transmitted and PCC voltage is increased. Table Ⅱ is the result of simulation and calculation.

 Figure 9 The simulation result of extinction angles per cycle.
 Figure 10 Min $r$ in one cycle.
 Figure 11 Firing angle order in inverter.
 Figure 12 Power of DC transmission.
 Figure 13 Line-to-ground RMS voltage of PCC.
Table Ⅱ Simulation and Calculation Result of Operating Point in SHD

When SHD occurs, since the CE introduces secondary harmonic currents into CEA, the inverter side CEA cannot track reference value. By reducing the output of CE, system is still capable of stable operation, while the output of CEA can better track the reference value. Besides, the transmission power is improved to some extent. Operating point calculation conforms to simulation results, indicating that calculation method has a certain practicality.

6 Conclusion

The probability of SHD increases in MIDC area. In this paper, HVDC control system operation characteristics in SHD are presented. The controller's improvement and a calculation method of HVDC operation point in SHD is proposed. Simulation results are given in the end, which match the mechanism and algorithm well, as described in the following.

1) When inverter bus SHD occurs, inverter natural commutation point shifts. PLL locks the fundamental phase in this situation, thus the sum of commutation angle and extinction angle changes.

2) SHD causes the periodic change of extinction angle. With the effect of CEA, the inverter side firing angle order value decreases, reducing the DC line transmission capacity and economic benefit. By moderately reducing the output of CE, an increased power transmission capacity and improved voltage stability can be achieved.

3) Quasi-steady-state model cannot describe the operating point of inverter when SHD occurs. New calculation method by setting firing angle order as parameter is proposed. Simulation results demonstrate the effectiveness of this method.

For future work, the operation of more power electronic elements in SHD should be considered, such as thyristor controlled series compensation (TCSC) and static VAR compensator (SVC) and the scheme will be applied to large-scale power systems.

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