2. 国家电网上海市电力公司信息通信公司 上海 200010;
3. 国家电网北京市电力公司 北京 100031
2. State Grid Shanghai Information and Telecommunication Company, Shanghai 200010, China;
3. State Grid Beijing Electric Power Company, Beijing 100031, China
Converter of high voltage direct current (HVDC) system turns into harmonic resource when it works with unbalanced AC voltage. Previous studies have focused on this phenomenon. According to [1], the 3rd harmonic current of inverter in international council on large electric systems (CIGRE) benchmark model can be as high as 0.469 kA in unbalanced situation. However, the operation of converter working in such serious harmonic distortion (SHD) condition lacks research, for the electrical coupling between converters is usually weak in the past. With the vigorous development of multiinfeed HVDC project in China, converters may be close to each other in HVDC placement area like Shanghai and Guangzhou. Possibility of converter working in SHD keeps growing in such areas [2]. Researches on converter operation in SHD are quite necessary.
Reference [3] analyzed the dynamic process of converter when asymmetrical problem happened in AC system, in which unbalanced conduction time and commutation angle between phases are considered. It calculated the harmonics generated by the converter. However, it did not elaborate the converter operation point calculation method. Reference [1] took the controller characteristic into consideration and found a way to calculate the operation point, but no further study on how other converters are affected by the harmonic current is proposed. Other studies on HVDC harmonics focused mainly on the transformation of harmonic order. Reference [4] analyzed transformation of converter bus harmonics in presence of harmonic voltage. Negative correlation between the dominant harmonic amplitude and phasechange angle is certified, however, only through simulation. References [5][7] determined the series relationship of harmonic impedance between DC and AC sides in HVDC system by defining DC and AC equivalence harmonic impedance, through which the frequency point resonance most likely to occur is calculated. However, only small signal model is applied in above references, where harmonics did not affect the operation point of DC system. There is no doubt that one converter will affect the control system of another by the harmonic current it generates. The operation point of the HVDC would be shifted as well. Numeric simulation software (PSCAD/EMTDC, etc.) can tell variety of DC/AC system characteristics under SHD. However, it is not enough to explain the inner theory of such phenomena.
In this paper, operation of HVDC system with SHD on converter bus is analyzed. Aiming the fact that constant extinction angle (CEA) controller cannot trace the setting value under SHD, an improved control scheme is proposed, with which steadystate error of CEA and power consumption in DC transmission are largely reduced. A calculation method of HVDC operation point in SHD is proposed in the end. The conclusion correctness is verified through PSCAD/EMTDC simulation.
2 Analysis of Converter Operation Working in SHDThe CIGREbenchmark model [8] applied in this paper is shown in Fig. 1. Inverter side SHD is created by paralleling harmonic power source beside the inverter bus. Constant current controller (CC), CEA controller and voltage dependent current order limited (VDCOL) controller constitute the control system.
According to [1] and [3], third harmonic current in AC side is the main harmonic order converter injection due to unbalanced AC voltage. Taking inverter bus voltage third harmonic as the objective, the following analysis focuses on SHD influence on HVDC system, including PLL and CEA controller. HVDC control system operation characteristics in SHD are then concluded. A calculation method of HVDC operation point in SHD is proposed in the end.
2.1 Analysis of Converter Bus Waveform in SHDThe expressions of converter bus voltage, also known as point of common coupling (PCC), with harmonics are in (1) [9]
$ \begin{align} &U_a=U_ 1\sin(\omega t)+\sum\limits_{h=2}U_h \sin(h\omega t+\phi_h) \nonumber\\ &U_b=U_ 1\sin(\omega t+120^{\circ})+\sum\limits_{h=2}U_h \sin(h\omega t+\phi_h+120^{\circ}) \nonumber\\ &U_c=U_ 1\sin(\omega t+240^{\circ})+\sum\limits_{h=2}U_h \sin(h\omega t+\phi_h+240^{\circ})\nonumber\\ \end{align} $  (1) 
where
With 3rd harmonic voltage distortion, the zero crossing points of phase
The shift of linetoline voltage zero crossing moment affects the actual size of extinction angle and commutation angle, which are determined by the operating characteristics of phase locked loop (PLL) in the converter firing angle controller.
2.2 Influence of Converter Bus SHD on PLLConverter firing controller is a control link which achieves operating status adjustment of converter commutation device. Currently, HVDC converter normally uses PLL control system [10]. The operating principle of PLL is shown in Fig. 3. The inserted error in normal operation is:
$ \begin{align} % \nonumber to remove numbering (before each equation) e=U_\alpha \cos(\theta)U_\beta \sin(\theta) \end{align} $  (2) 
where
$ \begin{array}{*{35}{l}} {}&{{U}_{\alpha \beta }}=T{{U}_{abc}}\text{ } \\ {}&{{U}_{\alpha \beta }}=\left[\begin{matrix} {{U}_{\alpha }} \\ {{U}_{\beta }} \\ \end{matrix} \right], \qquad T=\frac{2}{3}\left[\begin{matrix} 1&\frac{1}{2}&\frac{1}{2} \\ 1&\frac{\sqrt{3}}{2}&\frac{\sqrt{3}}{2} \\ \end{matrix} \right] \\ {}&{{U}_{abc}}=\left[\begin{matrix} {{U}_{a}} \\ {{U}_{b}} \\ {{U}_{c}} \\ \end{matrix} \right]. \\ \end{array} $  (3) 
When only fundamental wave component exists in converter bus voltage, with the above formula, inserted error can be expressed as:
$ \begin{align} % \nonumber to remove numbering (before each equation) e=U_1 \sin(\omega t\theta). \end{align} $  (4) 
In steady state,
$ \begin{align} % \nonumber to remove numbering (before each equation) e=U_1 \sin(\omega t\theta)+U_3 \sin(3\omega t+\phi_3\theta). \end{align} $  (5) 
In this state, the output theta tracks two components, respectively. The angular velocity
Fig. 4 displays that PLL output remains unchanged in SHD. Fig. 5 illustrates the small fluctuations of Fig. 4. The output component of harmonic voltage is insignificant when compared with the fundamental component. In the remaining part of the paper, the impact of the commutation bus distortion on PLL output will not be considered, assuming that the PLL still locks phase
The duration of some commutation process is increased by SHD, while others are decreased. This paper still uses the traditional 23 mode to describe this process, as is shown in Fig. 6.
In the commutation process, there is
$ \begin{align} \frac{dI_k}{dt}= \frac{U_aU_c}{2L_B}. \end{align} $  (6) 
In (6),
When 3rd voltage exists only, by substituting (1) into (6), we obtain (7)
$ \begin{align} \frac{dI_k}{dt}= \frac{\sqrt{6}U_1}{2L_B}\sin\left(\omega t \frac{\pi}{6}\right)+\frac{\sqrt{6}U_3}{2L_B}\sin\left(3\omega t\frac{\pi}{6}+\phi_3\right). \end{align} $  (7) 
For PLL still tracks the fundamental frequency, this paper sets the fundamental frequency angle as integration length. As for phase
$ \begin{align} I_d=& \int_{\frac{13\pi}{6}+\alpha}^{\frac{13\pi}{6}+\alpha +\mu} \bigg(\frac{\sqrt{6}U_1}{2L_B}\sin\left(\omega t\frac{\pi}{6}\right)\nonumber\\& +\frac{\sqrt{6}U_3}{2L_B}\sin\left(3\omega t\frac{\pi}{6}+\phi_3 \right)\bigg)d\omega t \end{align} $  (8) 
where
$ \begin{align} I_d=&\ \frac{\sqrt{6}U_1}{2X_B}[\cos(\alpha_I)\cos(\alpha_I +\mu)] \nonumber\\ & +\frac{\sqrt{6}U_1}{2X_B \times 3}\bigg[\cos\left(\frac{13\pi \times 3}{6}+3\alpha_I+\phi_3\right)\nonumber\\ &\cos\left(\frac{13\pi \times 3}{6}+3\alpha_I+\phi_3+3\mu\right)\bigg]. \end{align} $  (9) 
$ \begin{align} & {{I}_{d}}=\frac{\sqrt{6}{{U}_{1}}}{2{{X}_{B}}}[\cos (\alpha )\cos (\alpha +u)] \\ & +\sum\limits_{h=2}{\frac{\sqrt{6}{{U}_{h}}}{2{{X}_{B}}\times h}}[\cos (\left( \frac{\pi }{2}+m\times \frac{\pi }{3} \right) \\ & \times h+h\times \alpha +{{\phi }_{h}})\sum\limits_{h=2}{\cos }(\left( \frac{\pi }{2}+m\times \frac{\pi }{3} \right) \\ & \times h+h\times (\alpha +{{u}_{m}})+{{\phi }_{h}})] \\ \end{align} $  (10) 
where
When SHD happens, there is
$ \begin{equation}\label{2714910384} \gamma +\mu =180\alpha \Delta \alpha \end{equation} $  (11) 
where
Extinction angle
CEA aims at maintaining the extinction angle for a given value [12]. It is achieved by adjusting the inverter firing angle. The constant extinction angle controller CIGREbenchmark model used is structured as Fig. 7:
The inverter side firing angle has to decrease in SHD, so as to maintain the minimum of
$ \begin{align} &V_{do}=\frac{3\sqrt{2}}{\pi}BTE_{ac}\nonumber\\ &V_d=V_{do} \cos(\pi \alpha)+\frac{3}{\pi}X_c I_d B\nonumber\\ &\phi= {\arccos}\left(\frac{V_d }{V_{do}}\right)\nonumber\\ &P_d=V_d I_d\nonumber\\ &Q_d=P_d {\rm tan}(\phi). \end{align} $  (12) 
In (12),
By (12), one way to reduce the loss of transmission capacity is to minimize the decrease of inverter firing order.
The output of current error (CE) controller works as the interference for CEA, reflecting the impact of DC current on commutation process. By the switch function theory, when
It may moderately reduce the output of CE by multiplying it with coefficient m, where
In ACDC system load flow calculation, by using quasisteadystate model, the converter can be described as a PQ load. The only difference between pure AC system and ACDC system flow calculation is that DC element is added to the power equation.
Under the operation of constant current controller and CEA controller, the DC current and the extinction angle remain constant, so the corresponding elements of Jacobian matrix can be easily proposed. However, commutation changes in SHD, according to (10) and (11). The inverter side extinction angle changes periodically. In this case DC quasisteadystate model does not work well. New methods are needed to determine the operating point of the voltage distorted inverter.
Considering that the inverter side firing angle for fundamental voltage and power remains unchanged, (12) is able to describe the DC active and reactive power, this paper takes firing angle order as parameter in AC/DC flow calculation to get the operating point of the inverter station when distortion happens. Specific procedures are in Fig. 8.
When SHD happens, some of the commutation angles are elongated while others are shortened. Thus the extinction angles are correspondingly shortened and elongated. The simulation result of
Figs. 1013 illustrate simulation results of the minimum of
When SHD occurs, since the CE introduces secondary harmonic currents into CEA, the inverter side CEA cannot track reference value. By reducing the output of CE, system is still capable of stable operation, while the output of CEA can better track the reference value. Besides, the transmission power is improved to some extent. Operating point calculation conforms to simulation results, indicating that calculation method has a certain practicality.
6 ConclusionThe probability of SHD increases in MIDC area. In this paper, HVDC control system operation characteristics in SHD are presented. The controller's improvement and a calculation method of HVDC operation point in SHD is proposed. Simulation results are given in the end, which match the mechanism and algorithm well, as described in the following.
1) When inverter bus SHD occurs, inverter natural commutation point shifts. PLL locks the fundamental phase in this situation, thus the sum of commutation angle and extinction angle changes.
2) SHD causes the periodic change of extinction angle. With the effect of CEA, the inverter side firing angle order value decreases, reducing the DC line transmission capacity and economic benefit. By moderately reducing the output of CE, an increased power transmission capacity and improved voltage stability can be achieved.
3) Quasisteadystate model cannot describe the operating point of inverter when SHD occurs. New calculation method by setting firing angle order as parameter is proposed. Simulation results demonstrate the effectiveness of this method.
For future work, the operation of more power electronic elements in SHD should be considered, such as thyristor controlled series compensation (TCSC) and static VAR compensator (SVC) and the scheme will be applied to largescale power systems.
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